The present invention is related to a method and a device for examining quality of a dummy pattern insertion program that may be used in circuit (e.g., integrated circuit) and/or semiconductor device layout design.
For optimizing one or more of pattern density distribution, device performance uniformity, lithography, etching, chemical mechanical polishing (CMP), thermal anneal, stress, etc., in manufacturing a semiconductor device and/or integrated circuit, automatic dummy pattern insertion may be performed in a process of designing the layout of the semiconductor device using a dummy pattern insertion program (e.g., a script). Unsuitable dummy patterns in the layout of the semiconductor device may cause various issues, such as metal residual, device performance inconsistency, etc., in the manufacturing process. Therefore, quality of the dummy pattern insertion program may need to be examined.
Referring to FIG. 1, a method for examining the quality of a dummy pattern insertion program may include the following steps: designing or adjusting the dummy pattern insertion program, selecting a sample layout, using the dummy pattern insertion program to generate a dummy pattern according to the sample layout, inserting the dummy pattern into the sample layout to generate a dummy-inserted layout, and performing design rule check (DRC) on the dummy-inserted layout according to a set of design rules. If the dummy-inserted layout passes the design rule check, i.e., if the dummy-inserted layout complies with the design rules, then the dummy pattern insertion program may be approved for use in subsequent layout design processes. If the dummy-inserted layout fails the design rule check, then the dummy pattern insertion program may be adjusted (or updated). In general, the sample layout may not include sufficient (or comprehensive) reference layers. In addition, whether a dummy pattern design satisfies design rules may not be sufficiently checked. Therefore, even if a dummy pattern insertion program has been approved for use in layout design, the approved dummy pattern insertion program may generate and/or insert unsuitable dummy patterns. As a result, a layout that is designed using the approved dummy pattern insertion program may be defective.